View AD8352_362852.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Technical Data
FEATURES
-3 dB bandwidth of 2.0 GHz ( Av = 10 dB) Slew rate 11 V/ns Single resistor gain adjust 0 dB Av 24 dB Single resistor and capacitor distortion adjust Input resistance 3k , independent of gain Differential or single-ended input Low noise input stage 2.6 nV/Hz RTI @ AV = 10 dB Low distortion 19 MHz: -87dBc HD2, -90dBc HD3 71 MHz: -84dBc HD2, -84dBc HD3 180 MHz: -81dBc HD2, -80dBc HD3 OIP3 of 41 dBm to 180 MHz @ 2 V p-p out Fast settling and overdrive recovery Single-supply operation: 3 V to 5.0 V Low power dissipation 37 mA @ 5 V Power down capability 4 mA @ 5 V Fabricated on the XFCB3 process
2 GHz Ultralow Distortion Differential RF/IF Amplifier AD8352
FUNCTIONAL BLOCK DIAGRAM
ENB RGP RDP VIP RD VIN RDN
05728-001
05728-002
BIAS CELL
VCM VCC
+
VOP
RG
CD
-
VON
RGN
GND
AD8352
Figure 1.
-60 -65 -70 -75 44 42 40 38 36 34 32 DISTORTION VOUT = 2V p-p 200 LOAD 0 20 40 60 80 100 120 140 160 180 200 30 28 220
APPLICATIONS
Differential ADC driver Single-ended to differential conversion RF/IF gain blocks SAW filter interfacing
HD3 (dBc)
-80 -85 -90 -95 -100
FREQUENCY (MHz)
Figure 2. IP3 and Third Harmonic Distortion vs. Frequency
GENERAL DESCRIPTION
The AD8352 is a high performance differential amplifier for RF and IF applications to 500 MHz. It achieves 80 db SFDR at frequencies up to 180 MHz making it an ideal driver for high speed 14- and 16-bit A/D converters. Unlike other wideband differential amplifiers, the AD8352 has buffers that isolate the gain setting resistor (RG) from the signal inputs. As a result, the AD8352 maintains a constant 3 k input resistance for gains of 0 dB to 24 dB easing matching and input drive requirements. The AD8352 has a nominal 100 differential output resistance. The device is optimized for wide band, low distortion performance at frequencies beyond 500 MHz. These attributes, together with its wide gain adjust capability, make this device the amplifier of choice for general purpose IF and broadband applications where low distortion, noise, and power are critical. In particular, it is ideally suited for driving A/D converters (up to 16 bits), mixers, pin diode attenuators, and multielement discrete and SAW filters. The device comes in a compact 3 mm x 3 mm, 16-pin LFCSP package and operates over a temperature range of -40C to +85C.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
IP3 (dBm)
AD8352 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Noise Distortion Specifications .................................................. 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6
Preliminary Technical Data
Typical Performance Characteristics ..............................................7 Applications........................................................................................9 Gain Distortion and Adjustment ................................................9 Single-Ended Input to Differential Output Operation .......... 10 Loading Schemes........................................................................ 11 Evaluation Board ............................................................................ 12 Evaluation Board Schematics ................................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide........................................................................... 15
REVISION HISTORY
10/05--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
VS = 5 V, RL=200 differential, RG=100 (AV = 10 dB), f = 100 MHz, T = 25C; parameters specified differentially, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions Gain = 6 dB, VOUT 1.0 V p-p Gain = 12 dB, VOUT 1.0 V p-p Gain = 18 dB, VOUT 1.0 V p-p 6 dB gain 12 dB, VOUT 1.0 V p-p Using 1% resistor for RG, 0 dB AV 20 dB VS 5% -40C to +85C RL = 1 k, VOUT = 2 V step RL = 200 , VOUT = 2 V step 1 V step to 1% VIN = 4 V to 0 V step, VOUT 10 mV Min Typ 2,200 1,400 1,400 300 TBD TBD TBD 11 TBD <3 <2 TBD VCC/2 1.2 to 3.8 6 -60 TBD 20 TBD TBD -5 3 0.9 100 3 3 ENB 3 V ENB at 0.6 V ENB at 3 V ENB at 0.6 V 5 1.5 100 220 37 4.5 5.5 Max
AD8352
Unit MHz MHz MHz MHz dB dB/V mdB/C V/ns V/ns ns ns dB V V V p-p mV mV/C mV dB mV/C A k pF pF V V A A mA mA
Bandwidth for 0.2 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Common Mode Nominal Voltage Adjustment Range Maximum Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage CMRR Output Differential Offset Drift Input Bias Current Input Resistance Input Capacitance Single-Ended Output Resistance Output Capacitance POWER INTERFACE Supply Voltage ENB Threshold ENB Input Bias Current Quiescent Current
1 dB compressed Referenced to VCC/2 -40C to +85C
-40C to +85C
TBD
Rev. PrA | Page 3 of 16
AD8352
NOISE DISTORTION SPECIFICATIONS
Preliminary Technical Data
VS = 5 V, RL=200 differential, RG=100 (AV = 10 dB), T = 25C; parameters specified differentially, unless otherwise noted. Table 2.
Parameter 19 MHz 2nd/3rd Harmonic Distortion 1 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 71 MHz 2nd/3rd Harmonic Distortion1 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 100 MHz 2nd/3rd Harmonic Distortion Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 180 MHz 2nd/3rd Harmonic Distortion 2 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point
1
Conditions RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 1 k, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite
Min
Typ 87/90 83/84 92/87 84 42 2.6 13 84/84 83/83 TBD 85 41 2.6 13 83/82 80/82 TBD 86 41 2.6 13 81/82 79/82 TBD 82 40 2.6 13
Max
Unit dBc dBc dBc dBc dBm nV/Hz dBm dBc dBc dBc dBc dBm nV/Hz dBm dBc dBc dBc dBc dBm nV/Hz dBm dBc dBc dBc dBc dBm nV/Hz dBm
RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 1 k, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite f1 = 69.5 MHz, f2 = 70.5 MHz @ RL = 200
RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 1 k, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 100 MHz, f2 = 98 MHz, VOUT = 2 V p-p composite f1 = 100 MHz, f2 = 98 MHz
RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 1 k, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite f1 = 179 MHz, f2 = 180 MHz
3
5.5
When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini Circuits ADT1-1WT to obtain low frequency balance required for differential HD2 cancellation. 2 CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required.
Rev. PrA | Page 4 of 16
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage VCC Internal Power Dissipation JA1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec)
1
AD8352
Rating 5.5 V TBD TBD 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
See Applications section for single-ended to differential performance.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 16
AD8352 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 ENB 14 VCM 16 VIP
PIN 1 INDICATOR
Preliminary Technical Data
13 VCC
RDP 1 RGP 2 RGN 3 RDN 4
12 GND 11 VOP 10 VON 9 GND
AD8352
TOP VIEW (Not to Scale)
GND 7
GND 6
VCC 8
VIN 5
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6, 7, 9, 12 8, 13 10 11 14 Mnemonic RDP RGP RGN RDN VIN GND VCC VON VOP VCM Description Positive Distortion Adjust. Positive Gain Adjust. Negative Gain Adjust. Negative Distortion Adjust. Balanced Differential Input. Biased to VCM, typically ac-coupled. Ground. Connect to low impedence GND. Positive Supply. Balanced Differential Output. Biased to VCM, typically ac-coupled. Balanced Differential Output. Biased to VCM, typically ac-coupled. Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 F capacitor. With no reference applied, input and output common mode floats to midsupply = VCC/2. Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. Balanced Differential Input. Biased to VCM, typically ac-coupled.
15 16
ENB VIP
Rev. PrA | Page 6 of 16
05728-003
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
26 24 22 20 18 16 14 -3dB +12dB = 1.38GHz (dBc) -3dB +18dB = 1.4GHz -3dB +24dB = 844MHz -75 -77 -79 -81 -83 -85 -3dB +10dB = 1.9GHz -3dB +6dB = 2.2GHz -87 -89 -91 HD3 HD2
AD8352
GAIN (dB)
12 10 8 6 4 2 0 -2 -4 -6 10
05728-004
100
1k
10k
19
32
71 FREQUENCY (MHz)
100
180
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency for a 200 Differential Load (AV = 24, 18, 12, 10, and 6 dB)
-75 -77 -79 -81 (dBc) HD3 -83 -85 -87 -89 -91
Figure 7. Harmonic Distortion vs. Frequency for 2 V p-p into RL =1 k (AV = 10 dB, 5 V Supply) RG = 160 , RD = 6.8 k, CD = 0.1 pF
-76 >300MHz NO CD OR RD USED -78 2V p-p DISTORTION (dBc) -80 -82 -84 1V p-p -86 -88 -90
HD2
05728-005
19
32
71 FREQUENCY (MHz)
100
180
220
260
300
340
380
420
460
500
FREQUENCY (MHz)
Figure 5. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 200 (AV = 10 dB, 5 V Supply) RG = 100 , RD = 4.3 k, CD = 0.3 pF
26 24 22 20 18 -3dB 14 +12dB = 2.2GHz 12 10 8 6 4 2 0 -2 -4 -6 10 -3dB +6dB = 2.2GHz -3dB +10dB = 2.2GHz DISTORTION (dBc) 16 -3dB +18dB = 1.3GHz -3dB +24dB = 1.27GHz
Figure 8. Second-Order Harmonic Distortion HD2 vs. Frequency (AV = 10 dB, 5 V Supply)
-60 >300MHz NO CD OR RD USED -65 2V p-p -70
GAIN (dB)
-75
-80
1V p-p
-85
05728-006
100
1k
10k
220
260
300
340
380
420
460
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency for a 1 k Differential Load (AV = 24, 18, 12, 10, and 6 dB)
Figure 9. Third-Order Harmonic Distortion HD3 vs. Frequency (AV = 10 dB, 5 V Supply)
Rev. PrA | Page 7 of 16
05728-009
-90
05728-008
05728-007
AD8352
0 -10 -20 -30 -40 -50 AD8352 10dB GAIN DRIVING AD9445 14-BIT A/D CONVERTER ANALOG IN = 100MHz SNRFS = +68.8dB HD2 = -82.8dBc HD3 = -85.8dBc SFDR = +82.9dBc 0 -10 -20 -30 -40 -50
Preliminary Technical Data
AD8352 10dB GAIN DRIVING AD9445 14-BIT A/D CONVERTER ANALOG IN = 98MHz AND 101MHz 2f1-f2 = 88.5dBc 2f2-f1 = 83.9dBc
(XXX)
-70 -80 -90 -100 -110 -120
05728-010
(XXX)
-60
-60 -70 -80 -90 -100 -110 -120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Single Tone Distortion AD8352 Driving AD9445 (AV = 10 dB). See Figure 12.
Figure 11. Two Tone Distortion AD8352 Driving AD9445 (AV = 10 dB) Analog In = 98 MHz and 101 MHz. See Figure 12.
0.1F 0.1F IF/RF INPUT 0
16 1 2 11
14
0.1F
24
50 ADT1-1WT
CD
RD
RG
3 4 5
AD8352
10
AD9445
0.1F 24
05728-012
0.1F
0
Figure 12. External Circuit Configuration for Distortion Tests. See Figure 10 and Figure 11.
Rev. PrA | Page 8 of 16
05728-011
-130
-130
Preliminary Technical Data APPLICATIONS
GAIN DISTORTION AND ADJUSTMENT
Broadband selection of RG, CD, and RD for the AD8352 is optimized at frequencies of 180 MHz. These selections are listed at a 200 load in Table 5 and a 1 k load in Table 6. Figure 13 through Figure 16 show the plots for the RG and CD selections at the 200 and 1 k loads, respectively. Table 5. Broadband Selection of RG, CD, and RD: 200 Load
Gain 3 dB 6 dB 9 dB 12 dB 15 dB 18 dB RG 390 210 120 82 51 30 CD 0 pF 0.1 pF 0.2 pF 0.4 pF 0.7 pF 1 pF RD 6.8 k 4.3 k 4.3 k 4.3 k 4.3 k 4.3 k
1.0 0.9 0.8 0.7 0.6 CD (pF) 0.5 0.4 0.3 0.2 0.1 3 4 5 6 7 8 9
AD8352
10 11 12 13 14 15 16 17 18 GAIN (dB)
Figure 14. CD vs. Gain, RL = 200
700 600 500 400 300 200
Table 6. Broadband Selection of RG, CD, and RD: 1 k Load
Gain 3 dB 6 dB 9 dB 12 dB 15 dB 18 dB
400
RG 680 330 190 120 75 51
CD 0 pF 0 pF 0.1 pF 0.25 pF 0.5 pF 0.7 pF
RD 6.8 k 6.8 k 6.8 k 6.8 k 6.8 k 6.8 k
RG ()
100 350 300 250 RG () 200 150 100 50 0 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GAIN (dB)
05728-015 05728-016
0
Figure 15. RG vs. Gain, RL = 1 k
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 GAIN (dB)
Figure 13. RG vs. Gain, RL = 200
CD (pF)
05728-013
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 GAIN (dB)
Figure 16. CD vs. Gain, RL = 1 k
Rev. PrA | Page 9 of 16
05728-014
0
AD8352
SINGLE-ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION
The AD8352 can be configured as a single-ended to differential amplifier. To balance the outputs, when only driving the VIP input, an external resistor (RN) of 200 is added between VIP and RGN. Using the gain vs. frequency graph shown in Figure 18, RG can be selected for the desired gain and load. The distortion cancellation selection components, RD and CD, can be determined for the gain and load required (see Table 7 and Table 8). This configuration provides -3dB bandwidths similar to differential drives see Figure 4 and Figure 6. The distortion results (Figure 19 to Figure 22) were measured using a gain of 12 dB. Though not shown, the gains specified in Table 7 and Table 8 yield similar distortion results.
0.1F VIP RGP CD 0.1F AC
05728-024
Preliminary Technical Data
-60
-70 3RDS, 2V p-p OUT -80 (dBc) -90
-100
3RDS, 1V p-p OUT
10
70
140 FREQUENCY (MHz)
190
240
Figure 20. Single-Ended Third-Order Harmonic Distortion 200 Load.
-60
0.1F
50
50 RD RG
-70
AD8352
RGN
-80 (dBc)
RN 200 0.1F
25
2NDS, 2V p-p OUT -90
Figure 17. Single Ended Schematic
40 35
05728-023 05728-025
-100
2NDS, 1V p-p OUT
30 25
GAIN (dB)
-110
10
70
140 FREQUENCY (MHz)
190
240
20 15
GAIN, RL = 1k
-60
Figure 21. Single-Ended Second-Order Harmonic Distortion 1000 Load
GAIN, RL = 200 10
-70
5 0
-80 (dBc) 3RDS, 2V p-p OUT
1
10
100 (RG)
1k
10k
Figure 18. Gain vs. RG
-60
05728-020
-90
-100
-70 2NDS, 2V p-p OUT
3RDS, 1V p-p OUT
-110
-80
10
70
140 FREQUENCY (MHz)
190
240
(dBc)
2NDS, 1V p-p OUT -90
Figure 22. Single-Ended Third-Order Harmonic Distortion 1000 Load
-100
10
70
140 FREQUENCY (MHz)
190
240
Figure 19. AD8352 Single-Ended Second-Order Harmonic Distortion 200 Load
Rev. PrA | Page 10 of 16
05728-021
-110
05728-022
-110
Preliminary Technical Data
Table 7. Distortion Cancellation Selection Components RD and CD for Required Gain, 200 Load
Gain (dB) 3 6 9 12 15 18 RG () 4.3 k 520 200 100 62 43 CD (pF) 0 0 0.2 0.4 0.7 0.9 RD (k) 4.3 4.3 4.3 4.3 4.3 4.3
AD8352
LOADING SCHEMES
The AD8352 is characterized with two loads representing the most common ADC input resistance. The loads chosen are 200 and 1000 . These loads are accomplished using a broad band resistive match. The loading can be changed via R8, R9, and R12 giving the flexibility to characterize the AD8352 for the load in any given application. These loads are inherently lossy and thus must be accounted for in overall gain/loss for the evaluation board. Measure the gain of the AD8352 with an oscilloscope using the following procedure: 1. 2. 3. Measure the peak to peak voltage at the input node (C2 or C3), and Measure the peak to peak voltage at the out put node (C4 or C5), then Compute gain using the formula Gain = 20log VOUT/VIN Table 9. Typical Values Used for 200 and 1000 Loads
Component R8 R9 R12 200 Load 86.6 57.6 86.6 1000 Load 487 51.1 487
Table 8. Distortion Cancellation Selection Components RD and CD for Required Gain, 1000 k Load
Gain (dB) 6 9 12 15 18 RG () 3k 430 190 100 62 CD (pF) 0 0 0.2 0.3 0.5 RD (k) 4.3 4.3 4.3 4.3 4.3
Rev. PrA | Page 11 of 16
AD8352 EVALUATION BOARD
Preliminary Technical Data
An evaluation board is available for experimentation of various parameters such as gain, common mode level, and input and output network configurations can be modified through minor resistor changes. The schematic and evaluation board artwork are presented in Figure 23, Figure 24, and Figure 25. Table 10. Evaluation Board Circuit Components and Functions
Component Pin 8 to Pin 13 Name VCC Function Supply VCC = +5 V. Additional information
Pin 6, Pin 7, Pin 9, Pin 12 Pin 14, C9 RD/CD
GND
Connect to low impedance GND.
VCM, Capacitor Distortion Tuning Components ENB, Capacitor
Common Mode Offset Pin. Allows for monitoring or adjustment of the output common-mode voltage. C9 is a bypass capacitor. Distortion Adjustment components. Allows for third-order distortion adjustment HD3.
C9 = 0.1 F Typically, both are open above 300 MHz. CD = 0.3 pF, RD = 4.3 k (size 0402) Floats to 1.8 V to maintain device in power-up mode. C8 = 0.1 F T2 = MacomTM ETC1-1-13 R1 = open, R2 = 25 , R3 = 25 , R4 = 0 , R5 = 0 , R6 = 0 , C2 = 0.1 F, C3 = 0.1 F T2= MacomTM ETC1-1-13 R7 = 0 , R8 = 86.6 , R9 = 57.6 , R10 = open, R11 = 0 R12 = 86.6 , R13 = 0 , R14 = 0 , R15 = 0 C4 = 0.1 F, C5 = 0.1 F RG = 100 (Size 0402) for a gain of 10 dB C1 = 100 nF C6, C7 = 0.1 F Typically decoupled to ground using a 0.1 F capacitor with ac-coupled input/output ports.
Pin 15, C8
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. Pull down to disable. Can be bypassed and float high (1.8 V) for on state. C8 is a bypass capacitor. Input Interface. R1 and R4 ground one side of the differential drive interface for single-ended applications. T2 is a 1-to-1 impedance ratio balun to transform a single-ended input into a balanced differential signal. R2 and R3 provide a differential 50 input termination. R5 and R6 can be increased to reduce gain peaking when driving from a high source impedance. The 50 termination provides an insertion loss of 6 dB. C2 and C3 provide ac-coupling. Output Interface. R10, R13, R14, and R15 ground one side of the differential output interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun to transform a balanced differential signal to a single-ended signal. R8, R9, and R12 are provided for generic placement of matching components. R7 and R11 allow additional output series resistance when driving capacitive loads. The evaluation board is configured to provide a 150 to 50 impedance transformation with an insertion loss of 9.9 dB. C4 and C5 provide ac-coupling. R7 and R11 provide additional series resistance when driving capacitive loads. Gain Setting Resistor. Resistor RG is used to set the gain of the device. Refer to Table 5 and Table 6 when selecting the gain resistor. Power Supply Decoupling. The supply decoupling consists of a 100 nF capacitor to ground. C6 and C7 are bypass capacitors. Common Mode Offset Adjustment. Use Pin 14 to trim common-mode input/output levels. By applying a voltage to Pin 14, the input and output common-mode voltage can be directly adjusted.
R1,R2, R3, R4, R5, R6, T2, C2, C3
Resistors, Transformer, Capacitors
R7, R8, R9, R10, R11, R12, R13, R14 , R15, T1, C4, C5
Resistors, Transformer, Capacitors
RG C1, C6, C7 Pin 14
Resistor Capacitors VCM
Rev. PrA | Page 12 of 16
ENB R19 0 YELLOW SWITCH_SPDT R18 0 R20 0 VPOS C10 0.1F SW1 ENB BLACK VCM GND YELLOW
VCM
ENBL VCM
Preliminary Technical Data
EVALUATION BOARD SCHEMATICS
C8 0.1F VPOS
C9 0.1F
ENB
VCM
R1 OPEN
12 11 3 2 4
R2 25 GND VOP VON
10 9
RDP 1 16 RGP 2 CD 0.3pF RG 100 RGN 3 RDN 4 GND
5 6 7 8
15
14
VCC
VINP VIP
13
C2 0.1F R5 0 R7 0 C4 0.1F R8 86.6
VOUTP R14 OPEN
5 1
T2
1 5
RD 4.32k Z1
R9 57.6 R11 0 R12 86.6 C5 0.1F
T1
4 2 3
GND
Figure 23. Preliminary Characterization Board v.A01212A
Rev. PrA | Page 13 of 16
R4 0 R3 25 VPOS
C3 0.1F
R6 0
VIN
GND
VCC
VINN
M/A_COM ETC1-1-13
AD8352
M/A_COM ETC1-1-13
VOUTN R13 0
50 TRACES
HIGH IMPEDANCE TRACES (OPEN PLANES UNDER TRACES)
50 TRACES
J1 C11 0.1F
J2
VPOS RED
LOCATE CAPS NEAR DUT
VPOS
5 1 5 1
+
T3 T4 C12 0.1F
4 2 3 4 2 3
C1 10F
C6 0.1F
C7 0.1F
05728-017
AD8352
AD8352
Preliminary Technical Data
Figure 24. Component Side Silk Screen
Figure 25. Far Side showing Ground Plane Pull Back around critical features
Rev. PrA | Page 14 of 16
05728-019
05728-018
Preliminary Technical Data OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30
AD8352
PIN 1 INDICATOR
*1.65 1.50 SQ 1.35
13 12
16
EXPOSED PAD
1
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8352ACPZ-WP 1 AD8352ACPZ-RL71 AD8352-EVAL
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead LFCSP, Tube 16-Lead LFCSP, 7" Tape and Reel Evaluation Board
Package Option CP-16-3 CP-16-3
Z = Pb-free part.
Rev. PrA | Page 15 of 16
AD8352 NOTES
Preliminary Technical Data
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05728-0-10/05(PrA)
Rev. PrA | Page 16 of 16

▲Up To Search▲

Price & Availability of AD8352

	To Download AD8352 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .